1. Field of the Invention
The present invention relates to a high performance memory device, and in particular to semiconductor memory devices, for example Read Only Memory (ROM) devices, Flash devices, etc.
2. Description of the Prior Art
In such memory devices, a memory array is provided having a plurality of memory cells. Typically, the memory cells are arranged into a number of rows and columns, with the memory cells in a particular row being connected to a word line, and the memory cells in a particular column being connected to a bit line. To read the data state stored within a particular memory cell, the relevant word line is selected in order to turn on the relevant memory cell, and then the signal on the relevant bit line is monitored in order to detect the stored data state.
In one known prior art memory device, the bit lines are precharged prior to performing such a read operation. Thereafter, during the read operation, a particular memory cell identified by an address is accessed by selecting the appropriate word line and the appropriate bit line, and if the voltage on the selected bit line does not discharge, this indicates that a first data state is stored in the memory cell (for example a logic one level), whereas if the voltage on the selected bit line discharges, this indicates that a second data state is stored in the memory cell (for example a logic zero level).
Generally there is a continuing desire to make memory devices smaller and smaller, and as a result the sizes of the individual memory cells are becoming smaller and smaller. As the size of the memory cells decreases, the amount of leakage current from those memory cells increases, which leads to undesirable power consumption. With the aim of seeking to reduce such power consumption, it is known to provide techniques for selectively precharging only a subset of the bit lines, ideally only the bit line that is associated with the memory cell to be addressed, thereby avoiding leakage current that would occur through memory cells connected to other bit lines that are not of interest for the particular read operation to follow.
U.S. Pat. No. 6,282,136 describes one such selective pre-charge technique. FIG. 1 of the present application illustrates a memory device according to the teaching of U.S. Pat. No. 6,282,136. The memory array 40 consists of a plurality of memory cells 42, 44, . . . , 56, 58, which are arranged in a series of rows and columns. The program counter 10 transmits address signals to the memory device, and in particular sends address signals to the X-decoder 15 and the Y-decoder 20. The X-decoder selects a particular word line based on the received address. The Y-decoder 20 selects one of the pass transistors 32, 34, 36 within multiplexer logic 30 based on the address received from the program counter 10, thereby connecting one of the bit lines to the output circuit 60. The precharge transistor 64 is arranged to receive an inverted clock signal via the inverter 62, such that when the clock signal is high, the precharge transistor 64 turns on and precharges the bit line selected by the Y-decoder 20 via the multiplexer logic 30. Since the X-decoder 15 is driven by an inverted version of the clock signal, it only activates the relevant word line once the clock signal has gone low, by which time the required bit line will have been precharged by the precharge transistor 64.
U.S. Pat. No. 6,282,136 discusses the particular problem of ensuring that the address is decoded quickly enough to enable the relevant pass transistor in the multiplexer 30 to be turned on prior to the precharging operation taking place. With the aim of seeking to address this issue, the technique described in U.S. Pat. No. 6,282,136 sends the low order bit signals of the address to the X-decoder 15 and the upper order bit signals of the address to the Y-decoder 20. The memory array is arranged such that only the upper bits of the address are required by the Y-decoder 20 in order to choose the appropriate pass transistor 32, 34, 36, and accordingly there is sufficient time while the clock signal is high for the Y-decoder 20 to determine the appropriate pass transistor to turn on, and for that pass transistor to be turned on before the precharge transistor 64 is turned on to precharge the selected bit line, thereby avoiding a need to precharge any unnecessary bit lines, and hence reducing power consumption within the memory device.
Whilst such a technique can reduce power consumption, as the memory device is increased in size the capacitance exhibited by the multiplexer logic 30 increases, and this can significantly affect the speed with which the output circuit 60 can detect the stored data state within the addressed memory cell.
The Article “An 80-MOPS-Peak High-Speed and Low-Power Consumption 16-b Digital Signal Processor” by Hideyuki Kabuo et al., Pages 494 to 502, IEEE Journal of Solid State Circuits, Vol. 31, No. 4, April 1996, describes a digital signal processor (DSP), and on page 499 describes the data ROM used within that DSP. In a similar manner to that discussed earlier with reference to U.S. Pat. No. 6,282,136, this article describes with reference to FIG. 9 therein a technique whereby a particular bit line can be precharged prior to performing a read operation on the required memory cell, in accordance with the technique described therein a sense amplifier being used to detect the stored state in the addressed memory cell by monitoring the voltage on the selected bit line during the read operation. Whilst the use of sense amplifiers can provide an efficient technique for detecting the stored data state within the addressed memory cell, the speed of operation of the sense amplifier logic is significantly adversely affected by the capacitance of the multiplexer logic to which the sense amplifier logic is connected.
Accordingly, it would be desirable to provide a technique for improving the performance of reading a stored data state of memory cells within a memory device that uses precharging techniques to reduce power consumption.